The present invention relates to a plasma etching apparatus and method for applying a plasma processing to a substrate such as a semiconductor wafer.
In the manufacturing process of a semiconductor device, widely employed is a plasma etching treatment in which a plasma etching is applied to a target object or a semiconductor wafer (including a semiconductor wafer itself and a semiconductor wafer having a single film or a plurality of films formed thereon). Various types of plasma etching apparatuses are employed for the plasma etching treatment. Particularly, a capacitance coupling type parallel plate plasma processing apparatus is mainly used as the plasma etching apparatus.
In the capacitance coupling type parallel plate plasma etching apparatus, a pair of parallel plate electrodes (upper and lower electrodes) are arranged within a chamber a predetermined distance apart from each other to face each other. An etching gas is introduced into the chamber and, at the same time, a high frequency power is applied to one of the electrodes to form a high frequency electric field between the two electrodes. A plasma of the etching gas is formed by the high frequency electric field so as to apply a plasma etching to the semiconductor wafer.
Where a film formed on the semiconductor wafer, e.g., an oxide film, is etched by using the capacitance coupling type parallel plate plasma etching apparatus of the construction described above, a plasma of an intermediate density is formed by setting up an intermediate pressure within the chamber so as to make it possible to perform the optimum radical control. As a result, a suitable plasma state can be obtained so as to achieve an etching with a high selectivity ratio, with a high stability and with a high reproducibility.
To be more specific, it is described in “1997 DRY PROCESS SYMPOSIUM P385-390” that a high frequency of 27.12 MHz for plasma formation is applied to the upper electrode so as to form a plasma, and a high frequency of 800 kHz is applied to the lower electrode so as to draw the ions generated by the plasma onto the lower electrode, making it possible to perform a satisfactory etching under the pressure of 20 to 100 mTorr.
However, miniaturization of the design rule in USLI further proceeds in recent years, leading to demands for a higher aspect ratio in the shape of the hole. Under the conventional conditions, it is difficult to meet the requirement sufficiently.
The conventional plasma etching, in which a semiconductor wafer is disposed on the lower electrode, will now be described with reference to FIG. 8. A reference numeral 111 shown in the figure represents a resist layer acting as a mask for the selective etching. Reference numerals 112, 114 and 117 represent insulating films (SiO2 films), respectively. Further, reference numerals 113 and 115 represent an aluminum wiring and a gate wiring, respectively.
As shown in the figure, that portion of the resist layer 111 which is in the vicinity of a plasma sheath S is charged negative in the etching step, with the result that the electrons supplied from a plasma P are mainly moved in the lateral direction, resulting in failure to enter a contact hole 101 having a large aspect ratio. On the other hand, cations are accelerated by the plasma sheath so as to reach the bottom of the contact hole. As a result, the bottom portion (exposed portion of the aluminum wiring) 103 of the contact hole 101 is charged positive. On the other hand, both electrons and cations are accelerated to arrive at the space portion (exposed portion of the semiconductor wafer) 105 in which the contact hole is not formed without difficulty. As a result, a strong electric field is applied to the thin insulating film 117 positioned below the gate electrode 116 so as to bring about an insulation breakdown called shading damage.